1. Field of the Invention
The present invention relates to an improvement in a semiconductor device having an LDD (Light Doped Drain) structure.
2. Description of the Related Art
In a semiconductor device, elements have been more and more microminiaturized in a higher and higher packing density in recent years. The elements have been microminiaturized in accordance with the scaling law. In actual practice, however, this tendency is often not accompanied with the corresponding scaling of a power supply voltage. This is because it is necessary to make an associated integrated circuit TTL-compatible and its elements at a high operation speed type. It has been known that the absence of the attendant scaling of the power supply voltage exerts various adverse effects upon the semiconductor elements. There is, for example, a degradation in the characteristic of a MOSFET caused by a hot carrier. This is caused by a higher electric field in the vicinity of the drain in a MOSFET thus microminiaturized.
In the existing technique, a low impurity concentration area is provided in the vicinity of the drain and a side-wall LDD structure is employed so as to relax an electric field close to the drain. This is done so as to suppress the generation of a hot carrier and hence to improve the reliability of MOSFET's.
The manufacture of a side-wall LLD type n-MOSFET will be explained below by way of example.
FIGS. 1 to 3 show the method for the manufacture of a side-wall LLD type n-MOSFET.
As shown in FIG. 1, an oxide film 102 for elements isolation is created, by a selective oxidation method, in and on a p type silicon substrate 101. This provides an n-MOSFET's element area and its isolation area at the substrate 101. Further, a boron (B) ion 103 for threshold control is implanted, at an acceleration voltage of 20 [keV] and a dose of about 2.times.10.sup.12 [cm.sup.-2 ], into the element area of the n-MOSFET.
Then an about 10 [nm]-thick silicon oxide film 104 is formed, by a thermal oxidation method, on the element area of the n-MOSFET as shown in FIG. 2. An about 400 [nm]-thick polysilicon film 105 is deposited, by an LPCVD method, over the silicon oxide film 104. Then annealing is carried out, for about 30 minutes, in a POCl.sub.3 atmosphere at about 900.degree. C. to diffuse phosphorus (P) in the polysilicon film 105. As a result, the polysilicon film 105 becomes an n-type and a low ohmic state. Then the polysilicon film 105 is patterned by a photoetching method to provide a gate electrode 105. Then phosphorus (P) ion is implanted, at an acceleration voltage 50 [key] and a dose of about 7.times.10.sup.13 [cm.sup.-2 ], into the element area of the n-MOSFET with the gate electrode 105 used as a mask. A low concentration n.sup.- diffusion layer 106 is formed in the element area of the n-MOSFET. Then about 15 [nm]-thick thermal oxide film 107 is formed by the thermal oxidation method on the element area of n-MOSFET. This activates the phosphorous (P) in the n.sup.- diffusion layer 106 and prevents leakage of electric charges across the edge of the gate electrode 105 and the n.sup.- diffusion layer 106. Then about 150 [nm]-thick silicon oxide (SiO.sub.2) film 108 is formed on the whole surface of a resultant structure.
As shown in FIG. 3, the silicon oxide film 108 is etched, by an anisotropic etching, to leave the silicon oxide film 108 only on the side wall of the gate electrode 105. As a result, a side-wall oxide film 109 is provided on the side wall of the gate electrode 105. Using the gate electrode 105 and side-wall oxide film 109 as a mask, an arsenic (As) ion is implanted in the element area of n-MOSFET at an acceleration voltage of 40 [key] and a dose of about 5.times.10.sup.15 [cm.sup.-2 ], providing high concentration n.sup.+ diffusion layers (source and drain regions) 110. Annealing is effected for 30 minutes in an N.sub.2 atmosphere at about 850.degree. C. As a result, the arsenic in the n.sup.+ diffusion layer 110 is activated and the silicon substrate 101 can be recovered from a damage caused under the ion implantation process.
A metallization step, though being not shown, is performed, thus completing an n-MOSFET of a gate side-wall LLD structure.
According to the aforementioned manufacturing method, the n.sup.- diffusion layer 106 is formed nearer to the gate electrode by the thickness of the side-wall oxide film 109 with the n.sup.+ diffusion layer 110 as a reference. It is possible to form the n.sup.- diffusion layer 106 and n.sup.+ diffusion layer 110 in a self-aligned relation to the gate electrode. It is, therefore, possible to relax the concentration of an electric field in the vicinity of the drain region and to provide a MOSFET of high reliability.
In MOSFET manufactured by the aforementioned method, the hot carrier is suppressed by the low concentration n.sup.- diffusion layer and it is possible to implement a MOSFET of high reliability. There is, however, a drawback in that the operation speed of MOSFET is delayed due to a fall in drain current resulting from the parasitic resistance of the n.sup.- diffusion layer. Further, during the operation of MOSFET, charges are moved below the side-wall oxide film 109 due to the generation of a hot carrier. As a result, the n.sup.- diffusion layer below the side-wall oxide film 109 is depleted, resulting in an increase in resistance of the n.sup.- diffusion layer and a decrease in channel conductance gm and hence in a degeneration in the characteristic of MOSFET.
Further, there is a drawback from the standpoint of microminiaturizing elements, as will be set out below.
That is, provided that a MOSFET has a gate length of about 500 [nm] and a side-wall oxide film about 15 [nm] thick, the size of such MOSFET is increased by an amount corresponding to twice the thickness of the side-wall oxide film, that is about 30 [nm], compared with the case where a MOSFET has no such side-wall oxide film. As a result, the substantial size of the gate electrode is increased by about 30%, thus presenting a bar to the microminiaturization of a MOSFET.